Patent · US Active

On-chip test pattern generation

US10120026B2 · kind B2 · utility

1Cited by

12References

10Claims

0Family size

Assignee

LANTIQ BETEILIGUNGS-GMBH & CO. KG · DE

Inventors

Himanshu Kukreja · Singapore, SG
Shakil Ahmad · Singapore, SG

Key dates

Filing date	Oct 6, 2016
Grant date	Nov 6, 2018
Priority date	—
Expiry date	Dec 20, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/3187
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A chip is provided that includes an integrated circuit including a plurality of logic elements, wherein the plurality of logic elements is configured to form, in a test mode, a plurality of scan chains. The chip further includes an on-chip signal generator connected with the integrated circuit and configured to provide, in the test mode, a test pattern signal to the plurality of scan chains.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.