Eliminating redundant store instructions from execution while maintaining total store order
US10120686B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jun 7, 2016 |
| Grant date | Nov 6, 2018 |
| Priority date | — |
| Expiry date | Nov 28, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, and a binary translator. The binary translator includes circuitry to identify a redundant store in the instruction stream, mark the start and end of a region of the instruction stream with the redundant store, remove the redundant store, and store an amended instruction stream with the redundant store removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.