Vineeth Mekkat
13Patents
0h-index
26Co-inventors
40Inventor score
Filing activity: Mar 10, 2015 → May 19, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11693780B2 | System, method, and apparatus for enhanced pointer identification and prefetching | Physics | 0 | Active |
| US12216581B2 | System, method, and apparatus for enhanced pointer identification and prefetching | Physics | 0 | Active |
| US11080194B2 | System, method, and apparatus for enhanced pointer identification and prefetching | Physics | 0 | Active |
| US9996356B2 | Method and apparatus for recovering from bad store-to-load forwarding in an out-of-order processor | Physics | 0 | Active |
| US10915320B2 | Shift-folding for efficient load coalescing in a binary translation based processor | Physics | 0 | Active |
| US10540178B2 | Eliminating redundant stores using a protection designator and a clear designator | Physics | 0 | Active |
| US10228956B2 | Supporting binary translation alias detection in an out-of-order processor | Physics | 0 | Active |
| US10120686B2 | Eliminating redundant store instructions from execution while maintaining total store order | Physics | 0 | Active |
| US9710389B2 | Method and apparatus for memory aliasing detection in an out-of-order instruction execution platform | Physics | 0 | Active |
| US10853078B2 | Method and apparatus for supporting speculative memory optimizations | Emerging Cross-Sectional Technologies | 0 | Active |
| US10296343B2 | Hybrid atomicity support for a binary translation based microprocessor | Physics | 0 | Active |
| US10235177B2 | Register reclamation | Physics | 0 | Active |
| US9916164B2 | Methods and apparatus to optimize instructions for execution by a processor | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.