Configurable mailbox data buffer apparatus
US10120815B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2016 |
| Grant date | Nov 6, 2018 |
| Priority date | — |
| Expiry date | Jan 19, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/167
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single chip microcontroller has a master core and at least one slave core. The master core is clocked by a master system clock and the slave core is clocked by a slave system clock and wherein each core is associated with a plurality of peripheral devices to form a master microcontroller and a slave microcontroller, respectively. A communication interface is provided between the master microcontroller and the slave microcontroller, wherein the communication interface has a plurality of configurable directional data registers coupled with a flow control logic which is configurable to assign a direction to each of the plurality of configurable data registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.