Michael Catherwood
35Patents
10h-index
32Co-inventors
75Inventor score
Filing activity: Jul 5, 1990 → Apr 19, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5854944A | Method and apparatus for determining wait states on a per cycle basis in a data processing system | Physics | 44 | Expired |
| US5249280A | Microcomputer having a memory bank switching apparatus for accessing a selected memory bank in an external memory | Physics | 24 | Expired |
| US5249148A | Method and apparatus for performing restricted modulo arithmetic | Physics | 20 | Expired |
| US6728856B2 | Modified Harvard architecture processor having program memory space mapped to data memory space | Physics | 17 | Expired |
| US5890191A | Method and apparatus for providing erasing and programming protection for electrically erasable programmable read only memory | Physics | 15 | Expired |
| US6976158B2 | Repeat instruction with interrupt | Physics | 15 | Expired |
| US7966480B2 | Register pointer trap to prevent errors due to an invalid pointer value in a register | Physics | 12 | Active |
| US5680632A | Method for providing an extensible register in the first and second data processing systems | Physics | 12 | Expired |
| US5535376A | Data processor having a timer circuit for performing a buffered pulse width modulation function and method therefor | Physics | 10 | Expired |
| US5457802A | Integrated circuit pin control apparatus and method thereof in a data processing system | Emerging Cross-Sectional Technologies | 10 | Expired |
| US8495125B2 | DSP engine with implicit mixed sign operands | Physics | 5 | Active |
| US10248521B2 | Run time ECC error injection scheme for hardware validation | Physics | 5 | Active |
| US5598569A | Data processor having operating modes selected by at least one mask option bit and method therefor | Physics | 5 | Expired |
| US6604169B2 | Modulo addressing based on absolute offset | Physics | 3 | Expired |
| US7020788B2 | Reduced power option | Emerging Cross-Sectional Technologies | 3 | Expired |
| US6601160B2 | Dynamically reconfigurable data space | Physics | 2 | Expired |
| US7007172B2 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection | Physics | 2 | Expired |
| US8856406B2 | Peripheral trigger generator | Physics | 2 | Active |
| US8688964B2 | Programmable exception processing latency | Physics | 1 | Active |
| US8645729B2 | External device power control during low power sleep mode without central processing unit intervention | Emerging Cross-Sectional Technologies | 1 | Active |
| US9858083B2 | Dual boot panel SWAP mechanism | Physics | 1 | Active |
| US8984198B2 | Data space arbiter | Physics | 1 | Active |
| US9619231B2 | Programmable CPU register hardware context swap mechanism | Physics | 1 | Active |
| US6934728B2 | Euclidean distance instructions | Physics | 1 | Expired |
| US7243372B2 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection | Physics | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.