Methods and apparatuses for SW programmable adaptive bias control for speed and yield improvement in the near/sub-threshold domain
US10120967B2 · kind B2 · utility
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Key dates
| Filing date | Jul 21, 2015 |
| Grant date | Nov 6, 2018 |
| Priority date | — |
| Expiry date | Aug 31, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for implementing a Semiconductor Integrated Circuit device using Near/Sub-threshold technology with SW programmable adaptive and dynamic forward and reverse bias voltage control using different sensors inside the chip in order to improve speed, reduce leakage and ensure high yield of the final product that operates at an ultra-low power consumption. This method allows achieving ultra-low power solution with reasonable higher speed and insure high yield.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.