Detecting power loss in NAND memory devices
US10121551B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2017 |
| Grant date | Nov 6, 2018 |
| Priority date | — |
| Expiry date | Aug 31, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Devices and techniques for detecting power loss in NAND memory devices are disclosed herein. A memory controller may calibrate a first read level for a first physical page of a number of physical pages from an initial first read level position to a calibrated first read level position. The first read level may be between a first threshold voltage distribution corresponding to a first logical state of the at least four logical states and a second threshold voltage distribution corresponding to a second logical state of the at least four logical states. Also, the first threshold voltage distribution may be a highest threshold voltage distribution for the first physical page. The memory controller may calibrate a second read level for the first physical page that is lower than the first read level from an initial second read level position to a calibrated first read level position. The memory controller may determine to refresh at least one logical page stored at the first physical page based at least in part on a first read level difference between the initial first read level and the calibrated first read level and a second read level difference between the initial second read level…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.