Wear-limiting non-volatile memory
US10121555B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2016 |
| Grant date | Nov 6, 2018 |
| Priority date | — |
| Expiry date | Dec 10, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device having at least one non-volatile flash memory formatted with physical addresses to read and write data that is organized into blocks of data, wherein the blocks of data are organized into pages of data, and wherein the pages of data are organized into cells of data. The non-volatile memory device includes a non-volatile memory controller to direct read and write requests to the non-volatile flash memory for the storage and retrieval of data. The non-volatile memory controller includes a flash translation layer to correlate read and write requests for data having a logical address between the reading and writing the data to physical address location of the non-volatile flash memory. The flash translation layer, when writing to a physical address location, chooses between a wear-leveling circuit and a wear-limiting circuit to select the physical address location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.