In-kerf test structure and testing method for a memory array
US10121713B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2017 |
| Grant date | Nov 6, 2018 |
| Priority date | — |
| Expiry date | May 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/18
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed are an in-kerf test structure and testing method for testing an on-chip device. The structure includes at least one test component with at least one test device and adjoining dummy devices connected to the test device. Each adjoining dummy device has proximal node(s) directly connected to a test device and distal node(s) that are not directly connected to a test device. The nodes of each test device and the distal nodes of each adjoining dummy device are connected to input/output pads. During testing the input/output pads are used to bias the nodes of a selected test device as well as the distal node(s) of any adjoining dummy device. By biasing the distal node(s) of an adjoining dummy device, random accumulation of potential thereon is avoided and current contributions from the adjoining dummy device(s) to a current measurement taken from the selected test device can be accurately determined.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.