Method of manufacturing a semiconductor package
US10121774B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 11, 2016 |
| Grant date | Nov 6, 2018 |
| Priority date | — |
| Expiry date | Nov 10, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of inventive concepts disclosed provide a method of manufacturing a semiconductor package. The method includes mounting a plurality of semiconductor chips on a substrate having a connecting member protruding from a top surface of the substrate, applying a non-conductive paste on the substrate and the semiconductor chips, forming a supporting layer coupling each of the semiconductor chips to the substrate, aligning an interposer on the non-conductive paste, forming a non-conductive layer by applying heat while pressing the interposer and the substrate against each other, and cutting the substrate, the non-conductive layer, and the interposer into separate unit packages, each of which include a semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.