Elongated semiconductor structure planarization

US10121858B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Richard Kenneth Oxland · Brussels, BE
• Blandine Duriez · Brussels, BE
• Mark van Dal · Heverlee, BE
• Martin Christopher Holland · Leuven, BE

Key dates

• Filing date: Oct 30, 2015
• Grant date: Nov 6, 2018
• Expiry date: Oct 30, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/85
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

According to one example, a method includes epitaxially growing first portions of a plurality of elongated semiconductor structures on a semiconductor substrate, the elongated semiconductor structures running perpendicular to the substrate. The method further includes forming a gate layer on the substrate, the gate layer contacting the elongated semiconductor structures. The method further includes performing a planarization process on the gate layer and the elongated semiconductor structures, and epitaxially growing second portions of the plurality of elongated semiconductor structures, the second portions comprising a different material than the first portions.