Integrated magnetic random access memory with logic device
US10121964B2 · kind B2 · utility
13Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | Sep 23, 2015 |
| Grant date | Nov 6, 2018 |
| Priority date | — |
| Expiry date | Sep 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/10
Abstract
Integrating magnetic random access memory with logic is disclosed. The magnetic tunnel junction stack of a magnetic memory cell is disposed within a dielectric layer which serves as a via level of an interlevel dielectric layer with a metal level above the via level. An integration scheme for forming dual damascene structures for interconnects can be formed to logic and memory cells easily.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.