Patent · US Active

Wide frequency range delay locked loop

US10122369B2 · kind B2 · utility

0Cited by

1References

16Claims

0Family size

Assignee

Conversant Intellectual Property Management Inc. · CA

Inventors

Peter Vlasenko · Gatineau, CA
Dieter Haerle · Villach, AT

Key dates

Filing date	Apr 5, 2017
Grant date	Nov 6, 2018
Priority date	—
Expiry date	Apr 5, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/095
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.