Peter Vlasenko
29Patents
9h-index
10Co-inventors
72Inventor score
Filing activity: Nov 17, 1998 → Feb 9, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7336752B2 | Wide frequency range delay locked loop | Electricity | 58 | Expired |
| US6584003B1 | Low power content addressable memory architecture | Physics | 52 | Expired |
| US6717876B2 | Matchline sensing for content addressable memories | Physics | 28 | Expired |
| US7190201B2 | Method and apparatus for initializing a delay locked loop | Electricity | 19 | Expired |
| US6665220B2 | Column redundancy for content addressable memory | Physics | 18 | Expired |
| US6144591A | Redundancy selection circuit for semiconductor memories | Physics | 13 | Expired |
| US7532050B2 | Delay locked loop circuit and method | Electricity | 10 | Active |
| US7679418B2 | Voltage level shifter and buffer using same | Electricity | 9 | Active |
| US8599984B2 | Wide frequency range delay locked loop | Electricity | 9 | Active |
| US7915933B2 | Circuit for clamping current in a charge pump | Electricity | 6 | Active |
| US7285997B2 | Delay locked loop circuit and method | Electricity | 6 | Active |
| US7602222B2 | Power up circuit with low power sleep mode operation | Emerging Cross-Sectional Technologies | 5 | Expired |
| US8149032B2 | Circuit for clamping current in a charge pump | Electricity | 4 | Active |
| US7977985B2 | Bias generator providing for low power, self-biased delay element and delay line | Electricity | 2 | Active |
| US8213561B2 | Wide frequency range delay locked loop | Electricity | 2 | Active |
| US8411812B2 | Wide frequency range delay locked loop | Electricity | 2 | Active |
| US8000430B2 | Wide frequency range delay locked loop | Electricity | 2 | Active |
| US8704569B2 | Delay locked loop circuit and method | Electricity | 2 | Active |
| US8860480B2 | Circuit for clamping current in a charge pump | Electricity | 1 | Active |
| USRE43947E1 | Delay locked loop circuit and method | General | 1 | Active |
| US8125256B2 | Bias generator providing for low power, self-biased delay element and delay line | Electricity | 1 | Active |
| US8222930B2 | Power up circuit with low power sleep mode operation | Emerging Cross-Sectional Technologies | 0 | Active |
| US10122369B2 | Wide frequency range delay locked loop | Electricity | 0 | Active |
| US9360878B2 | Circuit for clamping current in a charge pump | Electricity | 0 | Active |
| US9917511B2 | Circuit for clamping current in a charge pump | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.