Hardware based map acceleration using forward and reverse cache tables
US10126964B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2017 |
| Grant date | Nov 13, 2018 |
| Priority date | — |
| Expiry date | May 25, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and method for managing map data in a data storage device. A programmable processor issues a find command to locate and place a requested map page of a map structure into a first cache to service a received host command. A non-programmable hardware circuit searches a forward table to determine whether the requested map page is in a second cache, and if so, loads the map page to the first cache. If not, the hardware circuit requests the requested map page from a back end processor which retrieves the requested map page from a non-volatile memory (NVM), such as a flash memory array. The hardware circuit searches a reverse table and the first cache to select a candidate location in the second cache for the retrieved requested map page from the NVM, and directs the storage of a copy of the requested map page at the candidate location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.