Inventor · Fort Collins, CO, US

Jackson L. Ellis

49Patents
13h-index
52Co-inventors
84Inventor score

Filing activity: Aug 6, 1990 → Mar 27, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US6336150B1 Apparatus and method for enhancing data transfer rates using transfer control blocks Physics 102 Expired
US6081849A Method and structure for switching multiple contexts in storage subsystem target device Physics 98 Expired
US6029226A Method and apparatus having automated write data transfer with optional skip by processing two write commands as a single write command Physics 78 Expired
US5907717A Cross-connected memory system for allocating pool buffers in each frame buffer and providing addresses thereof Electricity 61 Expired
US6247040A Method and structure for automated switching between multiple contexts in a storage subsystem target device Physics 55 Expired
US6449666B2 One retrieval channel in a data controller having staging registers and a next pointer register and programming a context of a direct memory access block Physics 34 Expired
US6324594A System for transferring data having a generator for generating a plurality of transfer extend entries in response to a plurality of commands received Physics 31 Expired
US6617893B1 Digital variable clock divider Electricity 29 Expired
US7461183B2 Method of processing a context for execution Physics 23 Expired
US5420994A Method for reading a multiple byte data element in a memory system with at least one cache and a main memory Physics 18 Expired
US8339891B2 Power savings and/or dynamic power management in a memory Emerging Cross-Sectional Technologies 18 Active
US7596639B2 Skip mask table automated context generation Physics 15 Expired
US7181548B2 Command queueing engine Physics 13 Expired
US6148326A Method and structure for independent disk and host transfer in a storage subsystem target device Physics 10 Expired
US8842480B2 Automated control of opening and closing of synchronous dynamic random access memory rows Physics 10 Active
US5434990A Method for serially or concurrently addressing n individually addressable memories each having an address latch and data latch Emerging Cross-Sectional Technologies 10 Expired
US5287512A Computer memory system and method for cleaning data elements Physics 9 Expired
US5835945A Memory system with write buffer, prefetch and internal caches Physics 6 Expired
US5953740A Computer memory system having programmable operational characteristics based on characteristics of a central processor Physics 5 Expired
US10140215B1 Low overhead mapping for highly sequential data Physics 5 Active
US6112278A Method to store initiator information for SCSI data transfer Physics 5 Expired
US8806112B2 Meta data handling within a flash media controller Physics 4 Active
US7613856B2 Arbitrating access for a plurality of data channel inputs with different characteristics Physics 4 Active
US7574541B2 FIFO sub-system with in-line correction Physics 4 Expired
US10126964B2 Hardware based map acceleration using forward and reverse cache tables Physics 3 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.