Caching data in a memory system having memory nodes at different hierarchical levels
US10127154B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Mar 20, 2013 |
| Grant date | Nov 13, 2018 |
| Priority date | — |
| Expiry date | Aug 1, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/604
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a plurality of memory nodes provided at different hierarchical levels of the memory system, each of the memory nodes including a corresponding memory storage and a cache. A memory node at a first of the different hierarchical levels is coupled to a processor with lower communication latency than a memory node at a second of the different hierarchical levels. The memory nodes are to cooperate to decide which of the memory nodes is to cache data of a given one of the memory nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.