Sheng Li
19Patents
5h-index
21Co-inventors
55Inventor score
Filing activity: May 21, 2010 → Apr 30, 2014
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9298621B2 | Managing chip multi-processors through virtual domains | Emerging Cross-Sectional Technologies | 12 | Active |
| US9620181B2 | Adaptive granularity row-buffer cache | Emerging Cross-Sectional Technologies | 9 | Active |
| US8788904B2 | Methods and apparatus to perform error detection and correction | Physics | 9 | Active |
| US10318365B2 | Selective error correcting code and memory access granularity switching | Physics | 5 | Active |
| US10152247B2 | Atomically committing write requests | Physics | 5 | Active |
| US9823986B2 | Memory node error correction | Physics | 3 | Active |
| US10621040B2 | Memory controllers to form symbols based on bursts | Physics | 2 | Active |
| US10572378B2 | Dynamic memory expansion by data compression | Physics | 2 | Active |
| US9952975B2 | Memory network to route memory traffic and I/O traffic | Physics | 2 | Active |
| US10572150B2 | Memory network with memory nodes controlling memory accesses in the memory network | Physics | 2 | Active |
| US10691344B2 | Separate memory controllers to access data in memory | Physics | 1 | Active |
| US8379879B2 | Active noise reduction system | Electricity | 1 | Active |
| US10127282B2 | Partitionable ternary content addressable memory (TCAM) for use with a bloom filter | Physics | 0 | Active |
| US10817178B2 | Compressing and compacting memory on a memory device wherein compressed memory pages are organized by size | Physics | 0 | Active |
| US10331560B2 | Cache coherence in multi-compute-engine systems | Physics | 0 | Active |
| US9832550B2 | Radix enhancement for photonic packet switch | Electricity | 0 | Active |
| US10241711B2 | Multiversioned nonvolatile memory hierarchy for persistent memory | Emerging Cross-Sectional Technologies | 0 | Active |
| US10402324B2 | Memory access for busy memory by receiving data from cache during said busy period and verifying said data utilizing cache hit bit or cache miss bit | Physics | 0 | Active |
| US10127154B2 | Caching data in a memory system having memory nodes at different hierarchical levels | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.