Patent · US Active

Circuit arrangement, network-on-chip and method for transmitting information

US10127171B2 · kind B2 · utility

1Cited by

5References

21Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Helmut Reinig · Isen, DE
Soeren Sonntag · Munich, DE

Key dates

Filing date	Sep 2, 2010
Grant date	Nov 13, 2018
Priority date	—
Expiry date	Dec 10, 2030

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A circuit arrangement, network-on-chip, and a method for transmitting information are disclosed. In one embodiment, an electrical circuit is provided comprising a plurality of circuit blocks comprising a first circuit block, a second circuit block, and a third circuit block, and a connection structure coupled to the plurality of circuit blocks, wherein the first circuit block is configured to send a request comprising information corresponding to the request and an address onto the connection structure, wherein the second circuit block is configured to initiate a transmission onto the connection structure in response to receiving the request, and wherein the third circuit block is configured to receive the transmission and wherein the address is assigned to the third circuit block.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.