Patent · US Active

Three transistor two junction magnetoresistive random-access memory (MRAM) bit cell

US10127961B2 · kind B2 · utility

1Cited by

2References

8Claims

0Family size

Assignees

IMEC VZW · BE
Katholieke Universiteit Leuven, KU LEUVEN R&D · BE

Inventors

Raf Appeltans · Haasrode, BE
Praveen Raghavan · Leefdaal, BE

Key dates

Filing date	Dec 2, 2016
Grant date	Nov 13, 2018
Priority date	—
Expiry date	Dec 2, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/1673
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Three transistor two junction magnetoresistive random-access memory (MRAM) bit cells provided. An example MRAM bit cell includes a first magnetic tunnel junction, MTJ, connected to a first bit line. The MRAM bit cell also includes a second MTJ connected to a second bit line. In addition, the MRAM bit cell includes a first transistor connected to the first MTJ and to a ground conductor. The MRAM bit cell further includes a second transistor connected to the second MTJ and to the ground conductor. Additionally, the MRAM bit cell includes a third transistor connected to the first transistor and to the second transistor.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.