Non-volatile memory (NVM) with dummy rows supporting memory operations
US10127990B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 18, 2017 |
| Grant date | Nov 13, 2018 |
| Priority date | — |
| Expiry date | Jul 18, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array includes rows and columns with memory cell portion and a dummy cell portion. Bit lines are connected to the memory cells and to the dummy cell portion. The dummy cell portion includes a first row of dummy cells and a second row of dummy cells. The dummy cells in the first row have a first connection to a corresponding bit line of a first bit line group of the bit lines and a second connection to a first source line. The dummy cells in the second row have a first connection to a corresponding bit line of a second bit line group of the plurality of bit lines and a second connection to a second source line. The dummy cells are selectively actuated to couple voltages at the first and second source lines to the first and second bit line groups, respectively, depending on memory operating mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.