Semiconductor structure and manufacturing method thereof
US10128113B2 · kind B2 · utility
2Cited by
0References
20Claims
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Assignee
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Key dates
| Filing date | Jan 12, 2016 |
| Grant date | Nov 13, 2018 |
| Priority date | — |
| Expiry date | Jan 12, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76807
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure comprises a substrate comprising an interlayer dielectric (ILD) and a silicon layer disposed over the ILD, wherein the ILD comprises a conductive structure disposed therein, a dielectric layer disposed over the silicon layer, and a conductive plug electrically connected with the conductive structure and extended from the dielectric layer through the silicon layer to the ILD, wherein the conductive plug has a length running from the dielectric layer to the ILD and a width substantially consistent along the length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.