Chen-Fa Lu
22Patents
4h-index
25Co-inventors
63Inventor score
Filing activity: Oct 10, 2000 → Mar 7, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6517413B1 | Method for a copper CMP endpoint detection system | Performing Operations; Transporting | 60 | Expired |
| US6555477B1 | Method for preventing Cu CMP corrosion | Electricity | 19 | Expired |
| US9793243B2 | Buffer layer(s) on a stacked structure having a via | Electricity | 15 | Active |
| US6524959B1 | Chemical mechanical polish (CMP) planarizing method employing derivative signal end-point monitoring and control | Performing Operations; Transporting | 4 | Expired |
| US10510723B2 | Buffer layer(s) on a stacked structure having a via | Electricity | 4 | Active |
| US8629053B2 | Plasma treatment for semiconductor devices | Electricity | 3 | Active |
| US10269701B2 | Semiconductor structure with ultra thick metal and manufacturing method thereof | Electricity | 2 | Active |
| US10128113B2 | Semiconductor structure and manufacturing method thereof | Electricity | 2 | Active |
| US11270978B2 | Buffer layer(s) on a stacked structure having a via | Electricity | 1 | Active |
| US8636559B2 | Method for wafer back-grinding control | Electricity | 0 | Active |
| US9418955B2 | Plasma treatment for semiconductor devices | Electricity | 0 | Active |
| US8716858B2 | Bump structure with barrier layer on post-passivation interconnect | Electricity | 0 | Active |
| US10134645B2 | Stress monitoring device and method of manufacturing the same | Electricity | 0 | Active |
| US12021066B2 | Buffer layer(s) on a stacked structure having a via | Electricity | 0 | Active |
| US8710458B2 | UV exposure method for reducing residue in de-taping process | Emerging Cross-Sectional Technologies | 0 | Active |
| US11670584B2 | Semiconductor structure with ultra thick metal and manufacturing method thereof | Electricity | 0 | Active |
| US8571699B2 | System and method to reduce pre-back-grinding process defects | Performing Operations; Transporting | 0 | Active |
| US10665456B2 | Semiconductor structure | Electricity | 0 | Active |
| US8298041B2 | System and method for wafer back-grinding control | Electricity | 0 | Active |
| US11114378B2 | Semiconductor structure with ultra thick metal and manufacturing method thereof | Electricity | 0 | Active |
| US9508659B2 | Method and apparatus to protect a wafer edge | Electricity | 0 | Active |
| US10534353B2 | System and method to reduce pre-back-grinding process defects | Performing Operations; Transporting | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.