Hybrid subtractive etch/metal fill process for fabricating interconnects
US10128185B2 · kind B2 · utility
3Cited by
12References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 13, 2017 |
| Grant date | Nov 13, 2018 |
| Priority date | — |
| Expiry date | Feb 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.