Patent · US Active

Package assembly having interconnect for stacked electronic devices and method for manufacturing the same

US10128221B2 · kind B2 · utility

0Cited by

1References

10Claims

0Family size

Assignee

Silergy Semiconductor Technology (Hangzhou) Ltd. · CN

Inventors

Xiaochun Tan · Bellevue, US
Jiaming Ye · Hangzhou City, CN

Key dates

Filing date	Jan 16, 2015
Grant date	Nov 13, 2018
Priority date	—
Expiry date	Mar 9, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/19107
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A package assembly and a method for manufacturing the same are disclosed. The package assembly includes a leadframe having at least two groups of leads and a plurality of electronic devices arranged in at least two levels. Each group of leads is electrically coupled to a respective level of electronic devices. The package assembly further includes an interconnect for coupling one or more leads of one group of leads to one or more leads of another group of leads. The package assembly results in increased packaging density, less usage of bonding wires in the package assembly, improves reliability, and prevents possible interference.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.