Pin diode structure having surface charge suppression
US10128297B2 · kind B2 · utility
1Cited by
1References
18Claims
0Family size
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Key dates
| Filing date | Nov 20, 2015 |
| Grant date | Nov 13, 2018 |
| Priority date | — |
| Expiry date | Nov 20, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/8023
Abstract
A semiconductor structure having: a silicon structure; and a plurality of laterally spaced PiN diodes formed in the silicon structure; and a surface of the silicon structure configured to reduce reverse bias leakage current through the PiN diodes. In one embodiment, a gate electrode structures is disposed on a surface of the silicon structure, the gate electrode structure having portions disposed between adjacent pairs of the diodes, the gate structure being biased to prevent leakage current through the diodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.