Hybrid SM3 and SHA acceleration processors
US10129018B2 · kind B2 · utility
3Cited by
6References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 12, 2015 |
| Grant date | Nov 13, 2018 |
| Priority date | — |
| Expiry date | Nov 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system includes a memory and a processing logic operatively coupled to the memory. The processing logic includes a message scheduling module selectively operating in one of a SHA mode or an SM3 mode to generate a sequence of message words based on an incoming message. The processing logic also includes a round computation module selectively operating in one of the SHA mode or the SM3 mode to perform at least one of a message expansion or a message compression based on at least one message word of the sequence of message words.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.