Vector mask driven clock gating for power efficiency of a processor
US10133577B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2012 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Jan 6, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes an instruction schedule and dispatch (schedule/dispatch) unit to receive a single instruction multiple data (SIMD) instruction to perform an operation on multiple data elements stored in a storage location indicated by a first source operand. The instruction schedule/dispatch unit is to determine a first of the data elements that will not be operated to generate a result written to a destination operand based on a second source operand. The processor further includes multiple processing elements coupled to the instruction schedule/dispatch unit to process the data elements of the SIMD instruction in a vector manner, and a power management unit coupled to the instruction schedule/dispatch unit to reduce power consumption of a first of the processing elements configured to process the first data element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.