Synchronous input/output (I/O) cache line padding
US10133691B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2016 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Oct 27, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method for synchronous input/output (I/O) cache line padding is described. The cache line padding occurs between a server having a processor executing an operating system and a recipient control unit. The method can include receiving, via the processor at the recipient control unit, a partial line direct memory access (DMA) write request; fetching, via the processor, a device table entry (DTE) associated with the partial line DMA write request; determining, via the processor, a cache line size for a synchronous input/output (I/O) cache line; and writing a full cache line DMA write request by padding, via the processor, the partial line DMA write request with a padded portion, where the padded portion is based on the cache line size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.