Inventor · Tillson, NY, US

Eric N. Lais

62Patents
6h-index
52Co-inventors
75Inventor score

Filing activity: Feb 18, 2000 → Mar 22, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US8495252B2 Implementing PCI-express memory domains for single root virtualized devices Physics 36 Active
US7035355B2 Apparatus and method for decode arbitration in a multi-stream multimedia system Electricity 25 Expired
US6922755B1 Directory tree multinode computer system Physics 19 Expired
US7440523B2 Apparatus and method for decode arbitration in a multi-stream multimedia system Electricity 16 Active
US8745292B2 System and method for routing I/O expansion requests and responses in a PCIE architecture Physics 8 Active
US8572635B2 Converting a message signaled interruption into an I/O adapter event notification Physics 7 Active
US8650335B2 Measurement facility for adapter functions Physics 6 Active
US8635430B2 Translation of input/output addresses to memory addresses Physics 6 Active
US8918573B2 Input/output (I/O) expansion response processing in a peripheral component interconnect express (PCIe) environment Physics 4 Active
US8650337B2 Runtime determination of translation formats for adapter functions Physics 4 Active
US8601497B2 Converting a message signaled interruption into an I/O adapter event notification Physics 3 Active
US7395375B2 Prefetch miss indicator for cache coherence directory misses on external caches Physics 3 Expired
US8645606B2 Upbound input/output expansion request and response processing in a PCIe architecture Physics 3 Active
US8615622B2 Non-standard I/O adapters in a standardized I/O architecture Physics 3 Active
US8769180B2 Upbound input/output expansion request and response processing in a PCIe architecture Physics 3 Active
US8417911B2 Associating input/output device requests with memory associated with a logical partition Physics 3 Active
US8631222B2 Translation of input/output addresses to memory addresses Physics 3 Active
US9336029B2 Determination via an indexed structure of one or more partitionable endpoints affected by an I/O message Physics 2 Active
US8250330B2 Memory controller having tables mapping memory addresses to memory modules Physics 2 Active
US9317442B2 Direct memory access (DMA) address translation with a consecutive count field Physics 2 Active
US8645767B2 Scalable I/O adapter function level error detection, isolation, and reporting Physics 2 Active
US10210131B2 Synchronous data input/output system using prefetched device table entry Physics 2 Active
US9483424B1 Peripheral component interconnect express (PCIE) pseudo-virtual channels and non-blocking writes Physics 2 Active
US12045471B2 Secure memory isolation for secure endpoints Physics 2 Active
US8261128B2 Selection of a domain of a configuration access Physics 2 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.