Priority based circuit synthesis
US10133840B2 · kind B2 · utility
0Cited by
3References
20Claims
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Assignee
Inventors
Key dates
| Filing date | Dec 4, 2015 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Mar 24, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method includes receiving, with one or more processors, a text-based description of a logic circuit comprising a plurality of logic sub-circuits, determining within the text-based description, with one or more processors, a set of circuit priority indicators for a corresponding set of the logic sub-circuits, and synthesizing, with one or more processors, the logic circuit according to the set of circuit priority indicators to provide a synthesized circuit description. A corresponding computer program product and computer system are also disclosed herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.