MRAM with metal-insulator-transition material
US10134459B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2016 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Oct 12, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory cells and methods for forming a memory cell are disclosed. The memory cell includes a first selector having a first gate coupled to a first word line (WL) and first and second source/drain (S/D) regions, and a second selector having a second gate coupled to a second WL and first and second S/D regions. The second S/D regions of the first and the second selectors are a common S/D region. The first and the second WLs are a common WL and the second S/D regions of the first and second selectors are coupled to a source line (SL). The memory cell includes a storage element which includes a magnetic tunnel junction (MTJ) element coupled with a bit line (BL) and the first and the second selectors, and a voltage control switch which includes a metal-insulator-transition (MIT) material coupled with the first selector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.