Independent state completion for each plane during flash memory programming
US10134474B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 20, 2017 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Oct 20, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5622
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a first plane of memory cells including an associated first buffer, a second plane of memory cells including an associated second buffer. The apparatus also includes a controller configured to transfer data corresponding to a first memory state the first buffer and transfer data corresponding to a second memory state to the second buffer. The apparatus also includes state machine configured to apply program pulses to the first and second planes of memory cells. The apparatus also includes read/write circuitry configured to independently confirm that the first and second planes of memory cells have reached the first and second memory states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.