Centralized built-in soft-repair architecture for integrated circuits with embedded memories
US10134483B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2016 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | May 16, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A large-scale integrated circuit with built-in self-repair (BISR) circuitry for enabling redundancy repair for embedded memories in each of a plurality of processor cores with embedded built-in self-test (BIST) circuitry. The BISR circuitry receives and decodes BIST data from the embedded memories into fail signature data in a physical-aware form on which repair analysis can be performed. The fail signature data is reformatted into a unified repair format, such that a fuse encoder circuit can be used to encode fuse patterns in that unified repair format for a repair entity for each of the embedded memories. The fuse patterns are reconfigured into the appropriate order for storing in shadow fuse registers associated with the specific embedded memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.