Devanathan Varadarajan
25Patents
6h-index
17Co-inventors
62Inventor score
Filing activity: Jul 20, 2005 → Dec 21, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7277803B2 | Efficient calculation of a number of transitions and estimation of power dissipation in sequential scan tests | Physics | 11 | Expired |
| US9053799B2 | Optimizing fuseROM usage for memory repair | Physics | 7 | Active |
| US10600495B2 | Parallel memory self-testing | Physics | 7 | Active |
| US10134483B2 | Centralized built-in soft-repair architecture for integrated circuits with embedded memories | Physics | 6 | Active |
| US9852810B2 | Optimizing fuseROM usage for memory repair | Physics | 6 | Active |
| US9318222B2 | Hierarchical, distributed built-in self-repair solution | Physics | 6 | Active |
| US8051347B2 | Scan-enabled method and system for testing a system-on-chip | Physics | 5 | Active |
| US7555687B2 | Sequential scan technique for testing integrated circuits with reduced power, time and/or cost | Physics | 3 | Expired |
| US11436090B2 | Non-volatile memory compression for memory repair | Electricity | 2 | Active |
| US9698779B2 | Reconfiguring an ASIC at runtime | Electricity | 2 | Active |
| US11373726B2 | Management of multiple memory in-field self-repair options | Physics | 1 | Active |
| US11568951B2 | Screening of memory circuits | Physics | 1 | Active |
| US7380184B2 | Sequential scan technique providing enhanced fault coverage in an integrated circuit | Physics | 0 | Expired |
| US11087857B2 | Enabling high at-speed test coverage of functional memory interface logic by selective usage of test paths | Physics | 0 | Active |
| US12283332B2 | Memory BIST circuit and method | Physics | 0 | Active |
| US12147697B2 | Methods and apparatus to characterize memory | Physics | 0 | Active |
| US11631472B2 | Built-in memory repair with repair code compression | Physics | 0 | Active |
| US12259789B2 | Non-volatile memory compression for memory repair | Electricity | 0 | Active |
| US11748202B2 | Non-volatile memory compression for memory repair | Electricity | 0 | Active |
| US12085610B2 | Methods and apparatus to identify faults in processors | Physics | 0 | Active |
| US12243603B2 | At-speed test of functional memory interface logic in devices | Physics | 0 | Active |
| US12009045B2 | Management of multiple memory in-field self-repair options | Physics | 0 | Active |
| US12217102B2 | Distributed mechanism for fine-grained test power control | Emerging Cross-Sectional Technologies | 0 | Active |
| US12033711B2 | Built-in memory repair with repair code compression | Physics | 0 | Active |
| US11881275B2 | Screening of memory circuits | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.