Low temperature atomic layer deposition of oxides on compound semiconductors

US10134585B2 · kind B2 · utility

Assignee

• The Regents of the University of California · US

Inventors

• Kasra Sardashti · Laguna Hills, US
• Tobin Kaufman-Osborn · Sunnyvale, US
• Tyler Kent · San Diego, US
• Andrew C. Kummel · San Diego, US
• Shariq Siddiqui · Albany, US
• Bhagawan Sahu · Watervliet, US
• Adam Brand · Palo Alto, US
• Naomi Yoshida · Sunnyvale, US

Key dates

• Filing date: Aug 19, 2015
• Grant date: Nov 20, 2018
• Expiry date: Aug 19, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/66
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Surface pretreatment of SiGe or Ge surfaces prior to gate oxide deposition cleans the SiGe or Ge surface to provide a hydrogen terminated surface or a sulfur passivated (or S—H) surface. Atomic layer deposition (ALD) of a high-dielectric-constant oxide at a low temperature is conducted in the range of 25-200° C. to form an oxide layer. Annealing is conducted at an elevated temperature. A method for oxide deposition on a damage sensitive III-V semiconductor surface conducts in-situ cleaning of the surface with cyclic pulsing of hydrogen and TMA (trimethyl aluminum) at a low temperature in the range of 100-200° C. Atomic layer deposition (ALD) of a high-dielectric-constant oxide forms an oxide layer. Annealing is conducted at an elevated temperature. The annealing can create a silicon terminated interfaces.