Semiconductor device and method
US10134604B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2017 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Oct 5, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.