Semiconductor chip, semiconductor package including the same, and method of manufacturing semiconductor chip
US10134702B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2017 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Apr 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (TSV) structures in the pad region. The plurality of uppermost wirings may extend in parallel along one direction and have a same width. The passivation layer may cover at least a top surface of the plurality of uppermost wirings in the cell region and includes a top surface having a wave shape.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.