Warpage control of semiconductor die package
US10134706B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2017 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Aug 14, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various embodiments of mechanisms for forming a die package using a compressive dielectric layer to contact and to surround through substrate vias (TSVs) in the die package are provided. The compressive dielectric layer reduces or eliminates bowing of the die package. As a result, the risk of broken redistribution layer (RDL) due to bowing is reduced or eliminated. In addition, the compressive dielectric layer, which is formed between the conductive TSV columns and surrounding molding compound, improves the adhesion between the conductive TSV columns and the molding compound. Consequently, the reliability of the die package is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.