Inventor · Hsinchu, TW

Kuo Lung Pan

66Patents
5h-index
51Co-inventors
71Inventor score

Filing activity: Sep 12, 2012 → Nov 1, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US9059107B2 Packaging methods and packaged devices Electricity 15 Active
US9508674B2 Warpage control of semiconductor die package Electricity 11 Active
US10978382B2 Integrated circuit package and method Electricity 8 Active
US11508656B2 Semiconductor package and method Electricity 7 Active
US9620465B1 Dual-sided integrated fan-out package Electricity 5 Active
US10134706B2 Warpage control of semiconductor die package Electricity 5 Active
US10658258B1 Chip package and method of forming the same Electricity 4 Active
US9935081B2 Hybrid interconnect for chip stacking Electricity 4 Active
US10847505B2 Multi-chip semiconductor package Electricity 4 Active
US11183487B2 Integrated circuit package and method Electricity 4 Active
US9773749B2 Warpage control of semiconductor die package Electricity 3 Active
US9735130B2 Chip packages and methods of manufacture thereof Electricity 3 Active
US10461023B2 Semiconductor packages and methods of forming the same Electricity 3 Active
US11502013B2 Integrated circuit package and method Electricity 3 Active
US9607959B2 Packaging device having plural microstructures disposed proximate to die mounting region Electricity 2 Active
US11201118B2 Chip package and method of forming the same Electricity 2 Active
US11049805B2 Semiconductor package and method Electricity 2 Active
US11424213B2 Semiconductor structure including a first surface mount component and a second surface mount component and method of fabricating the semiconductor structure Electricity 2 Active
US9666530B1 Semiconductor device Electricity 2 Active
US11764171B2 Integrated circuit structure and method Electricity 1 Active
US11444002B2 Package structure Electricity 1 Active
US11508665B2 Packages with thick RDLs and thin RDLs stacked alternatingly Electricity 1 Active
US11495590B2 Multi-chip semiconductor package Electricity 1 Active
US11848300B2 Semiconductor structure including a semiconductor wafer and a surface mount component overhanging a periphery of the semiconductor wafer Electricity 1 Active
US11694966B2 Chip package and method of forming the same Electricity 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.