Method of forming two-dimensional and three-dimensional semiconductor chip arrays
US10134793B1 · kind B1 · utility
2Cited by
2References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 16, 2017 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | May 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54426
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A sensor chip formed from a plurality of sensor chips fabricated on a wafer, the wafer including a top surface, a bottom surface opposite the top surface and a thickness between the top and bottom surfaces, the sensor chip including an active area formed on the top surface, a first sacrificial edge including a first fiducial and a second fiducial, and a first score line formed in a first portion of the thickness on the top surface between the first sacrificial edge and the active area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.