Porous silicon post processing
US10134837B1 · kind B1 · utility
137Cited by
8References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2017 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Jun 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor on insulator (SOI) device may include a semiconductor handle substrate. The semiconductor hand may include a porous semiconductor layer, and an etch stop layer proximate the porous semiconductor layer. The SOI may also include an insulator layer on the etch stop layer. The SOI may further include a device semiconductor layer on the insulator layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.