Patent · US Active

Semiconductor device having a dielectric layer with different thicknesses and method for forming

US10134860B2 · kind B2 · utility

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6References
18Claims
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Key dates

Filing dateMar 13, 2017
Grant dateNov 20, 2018
Priority date
Expiry dateMar 13, 2037

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D64/111

Abstract

A semiconductor device includes a first dielectric layer on a substrate, the first dielectric layer including a first dielectric portion over a first doped well region of a first conductivity type and a second dielectric portion over a second doped well region of a second conductivity type, and a second dielectric layer on the substrate directly adjacent the first dielectric layer. The second dielectric layer is over the second doped well region. A first conductive gate structure is over the first and second dielectric layers. A third dielectric layer is on the substrate over the second doped well region and separated a first distance from the second dielectric layer. A second conductive gate structure is over the third dielectric layer. A third doped region of the second conductivity type is implanted in the second doped well region a second distance from the third dielectric layer and the second conductive gate structure.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.