Semiconductor memory device, memory system including the same, and method of error correction of the same
US10140176B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2016 |
| Grant date | Nov 27, 2018 |
| Priority date | — |
| Expiry date | May 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1575
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An error correcting method of a semiconductor memory device includes receiving first data from outside the semiconductor memory device. First check bits are generated based on the first data and a first parity generator matrix. The first parity generator matrix includes a plurality of columns of bits. The plurality of columns of bits are arranged in a plurality of parity generator matrix groups. An error correcting code (ECC) code word including a plurality of ECC code word groups is stored in the plurality of memory cell groups. Each of the plurality of ECC code word groups have the first data and the first check bits. The plurality of ECC code word groups correspond to the plurality of parity generator matrix groups, respectively. For each parity generator matrix group of the first parity generator matrix, a result value of a bit-by-bit exclusive OR (XOR) operation performed on any two columns included in the parity generator matrix group is equal to a column number of a column that is not included in the parity generator matrix group. Thus, when a first ECC code word group, from among the plurality of ECC code word groups, includes error bits, a miscorrected bit that would be ca…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.