Hoiju Chung
30Patents
3h-index
27Co-inventors
59Inventor score
Filing activity: Nov 14, 2011 → Oct 6, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8996759B2 | Multi-chip memory devices and methods of controlling the same | Physics | 4 | Active |
| US9583215B2 | Semiconductor memory device and testing method thereof | Physics | 4 | Active |
| US10915398B2 | Memory system and operating method thereof | Electricity | 3 | Active |
| US11322219B2 | Memory system, integrated circuit system, and operation method of memory system | Physics | 3 | Active |
| US10884848B2 | Memory device, memory system including the same and operation method of the memory system | Physics | 3 | Active |
| US10284198B2 | Memory systems with ZQ global management and methods of operating same | Physics | 2 | Active |
| US11030040B2 | Memory device detecting an error in write data during a write operation, memory system including the same, and operating method of memory system | Physics | 2 | Active |
| US10140176B2 | Semiconductor memory device, memory system including the same, and method of error correction of the same | Electricity | 1 | Active |
| US10311936B2 | Semiconductor memory device managing flexible refresh skip area | Physics | 1 | Active |
| US10198851B2 | Rendering system and method | Physics | 1 | Active |
| US11024402B2 | Memory system and operation method thereof | Physics | 1 | Active |
| US11188417B2 | Memory system, memory module, and operation method of memory system | Electricity | 1 | Active |
| US10810080B2 | Memory device selectively correcting an error in data during a read operation, memory system including the same, and operating method of memory system | Physics | 1 | Active |
| US11887650B2 | Semiconductor memory device managing flexible refresh skip area | Physics | 0 | Active |
| US12190934B2 | Memory with row hammer mitigation technique | Physics | 0 | Active |
| US11657890B2 | Memory system, integrated circuit system, and operation method of memory system | Physics | 0 | Active |
| US12027193B2 | Memory device for performing smart refresh operation by counting received address | Physics | 0 | Active |
| US11747985B2 | Memory system, integrated circuit system, and operation method of memory system | Physics | 0 | Active |
| US11537467B2 | Memory, memory system, and operation method of memory | Physics | 0 | Active |
| US11475936B2 | Memory and memory system | Physics | 0 | Active |
| US11265022B2 | Memory system and operating method thereof | Electricity | 0 | Active |
| US11631449B2 | Semiconductor memory device managing flexible refresh skip area | Physics | 0 | Active |
| US11442810B2 | Memory and operation method of memory | Electricity | 0 | Active |
| US12249386B2 | Memory, memory system and operation method of memory system | Physics | 0 | Active |
| US12099411B2 | Error processing circuit, memory and operation method of the memory | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.