Low overhead mapping for highly sequential data
US10140215B1 · kind B1 · utility
Inventors
Key dates
| Filing date | May 26, 2017 |
| Grant date | Nov 27, 2018 |
| Priority date | — |
| Expiry date | May 26, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.