Hardware node with matrix-vector multiply tiles for neural network processing
US10140252B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2017 |
| Grant date | Nov 27, 2018 |
| Priority date | — |
| Expiry date | Jun 29, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Hardware and methods for neural network processing are provided. A method in a system comprising a plurality of nodes, where each node comprises a plurality of tiles, is provided. The method includes receiving an N by M matrix of coefficients configured to control a neural network model. The method includes storing a first row and a second row of the N by M matrix of coefficients in a first and a second on-chip memories incorporated within a first and a second of the plurality of tiles. The method includes processing the first row of the coefficients and a first set of input vectors using a first compute unit incorporated within the first of the plurality of tiles. The method includes processing the second row of the coefficients and a second set of input vectors using a second compute unit incorporated within the second of the plurality of tiles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.