Patent · US Active

Memory bandwidth management for deep learning applications

US10140572B2 · kind B2 · utility

3Cited by

3References

20Claims

0Family size

Assignee

MICROSOFT TECHNOLOGY LICENSING, LLC · US

Inventors

Ray Bittner · Bothell, US
Frank Torsten Bernd Seide · Aachen, DE

Key dates

Filing date	Jun 25, 2015
Grant date	Nov 27, 2018
Priority date	—
Expiry date	Dec 30, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG10L15/16
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In a data center, neural network evaluations can be included for services involving image or speech recognition by using a field programmable gate array (FPGA) or other parallel processor. The memory bandwidth limitations of providing weighted data sets from an external memory to the FPGA (or other parallel processor) can be managed by queuing up input data from the plurality of cores executing the services at the FPGA (or other parallel processor) in batches of at least two feature vectors. The at least two feature vectors can be at least two observation vectors from a same data stream or from different data streams. The FPGA (or other parallel processor) can then act on the batch of data for each loading of the weighted datasets.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.