Multiple register memory access instructions, processors, methods, and systems
US10141033B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2017 |
| Grant date | Nov 27, 2018 |
| Priority date | — |
| Expiry date | Dec 27, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30163
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.