Erasing method of single-gate non-volatile memory
US10141057B1 · kind B1 · utility
1Cited by
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3Claims
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Key dates
| Filing date | Nov 21, 2017 |
| Grant date | Nov 27, 2018 |
| Priority date | — |
| Expiry date | Nov 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erasing method of a single-gate non-volatile memory is provided. The single-gate non-volatile memory has a single floating gate. The erasing method includes applying a voltage to the drain without applying to the gate to create and control an inversion layer. Therefore the required erasing voltage is reduced and the erasing speed is improved to avoid the over-erase problem.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.